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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
LOW VOLTAGE TELEPHONE TRANSMISSION CIRCUIT WITH DIALLER INTERFACE
DESCRIPTION
The UTC TEA1062N / TEA1062AN is a bipolar integrated circuit performing all speech and line interface function, required in the fully electronic telephone sets. It performs electronic switching between dialing speech. The circuit is able to operate down to D.C. line voltage of 1.6V (with reduced performance) to facilitate the use of more telephone sets in parallel.
SOP-16
DIP-16
FEATURES
* Low d.c. line voltage; operates down to 1.6V (excluding polarity guard). *Voltage regulator with adjustment static resistance. *Provides supply with limited current for external circuitry. *Symmetrical high-impedance inputs (64k) for dynamic, magnetic or piezoelectric microphones. *Asymmetrical high-impedance inputs (32k) for electret microphones. *DTMF signal input with confidence tone. *Mute input for pulse or DTMF dialing. *Receivering amplifier for several types of earphones. *Large amplification setting range on microphone and earpiece amplifiers. *Line loss compensation facility , line current depedant (microphone and earpiece amplifiers). *Gain control adaptable to exchange supply. *Possibility to adjust the d.c. line voltage.
QUICK REFERENCE DATA
Line voltage at Iline=15mA Line current operating range[pin1] normal operation with reduced performance Internal supply current Supply current for peripherials at Iline=15 mA MUTE input LOW(1062 is HIGH) VCC>2.2V VCC>2.8V Voltage amplification range microphone amplifier receiving amplififer Line loss compansation Amplification control range Exchange supply voltage range Exchange feeding bridge resistance range Operating ambient temperature range VLN Iline Iline ICC typ. 3.8 V 11 to 140 mA 1 to 11 mA typ. 1mA
Ip Ip AVD AVD AVD Vexch Rexch Tamb
typ. typ.
1.8mA 0.7mA
44 to 52 dB 20 to 39 dB typ. 6 dB 36 to 60V 400 to 1000 -25 to +75C
UTC
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QW-R108-011,A
UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
VCC 13 LN 1 5 IR 10 4 QR GAR
MIC+ 7 MIC6
2 GAS1
3 GAS2 DTMF 11
dB
MUTE 12 SUPPLY AND REFERENCE CONTROL CURRENT CURRENT REFERENCE 9 VEE 14 REG 15 AGC 8 STAB LOW VOLTAGE CIRCUIT
16 SLPE
Fig.1
Block Diagram
LN
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
SLPE AGC
GAS1 GAS2 QR GAR MICMIC+ STAB
REG VCC MUTE DTMF IR VEE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
LN GAS1 GAS2 QR GAR MICMIC+ STAB VEE IR DTMF MUTE Vcc REG AGC SLPE
positive line terminal gain adjustment; transmitting amplifier gain adjustment; transmitting amplifier non-inverting output,receiving amplifier gain adjustment; receiving amplifier inverting microphone input on-inverting microphone input current stabilizer negative line terminal receiving amplifier input dual-tone multi-frequency input mute input positive supply decoupling voltage regulator decoupling automatic gain control input slope (DC resistance) adjustment
Fig.2
PIN CONFIGURATIONS
UTC
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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Positive Continuous Line Voltage Repetitive Line Voltage During Switch-On Or Line Interruption Repetitive Peak Line Voltage for a 1 ms Pulse/5s
TEST CONDITIONS SYMBOL
VLN VLN R10=13 R9=20 (see Fig.15) R9=20
MIN
MAX
12 13.2
UNIT
V V
VLN 28 V Iline 140 mA Vi VCC+0.7 V -Vi 0.7 V R9=20 Total Power Dissipation (2) Ptot 640 mW C Storage Temperature Range Tstg -40 +125 C Operating Ambient Temperature Range Tamb -25 +75 C Junction Temperature Tj +125 1. Mostly dependent on the maximum required Tamb and the voltage between LN and SLPE (see Figs 6 ). 2. Calculated for the maximum ambient temperature specified Tamb=75C and a maximum junction temperature of 125C. Line Current (1) Voltage on All Other Pins
THERMAL RESISTANCE
From junction to ambient in free air Rth j-a = 75K/W
ELECTRICAL CHARACTERISTICS (Iline=11 to 140mA;VEE=0V;f=800Hz;Tamb=25C; unless otherwise
specified)
PARAMETER Supply; LN and VCC(pins 1 and 13)
Voltage Drop Over Circuit, between LN and VEE
TEST CONDITIONS
SYMBOL
MIN
TYP
MAX
UNIT
Variation with Temperature Voltage Drop Over Circuit, between LN and VEE with External Resistor RVA
MIC inputs open Iline=1mA Iline=4mA Iline=15mA Iline=100mA Iline=140mA Iline=15mA Iline=15mA RVA(LN to REG) =68k Iline=15mA RVA(REG to SLPE) =39k VCC=2.8V Iline=15mA Ip=1.2mA; MUTE=HIGH lp=0mA;MUTE=HIGH Ip=1.2mA; MUTE=LOW lp=0mA;MUTE=LOW
VLN VLN VLN VLN VLN VLN/T
3.55 4.9
1.6 1.9 4.0 5.7 -0.3
4.25 6.5 7.5
V V V V V mV/K
3.5
V
4.5 ICC 0.9 1.35
V mA
Supply Current Supply Voltage Available for Peripheral Circuitry TEA1062N TEA1062AN
VCC VCC VCC VCC
2.2 2.2
2.7 3.4 2.7 3.4
V V V V
UTC
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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS (continued)
PARAMETER TEST CONDITIONS Microphone inputs MIC+ and MIC- (pins 6 and 7)
Input impedance (differential) between MIC- and MIC+ Input impedance (sigle-ended) MIC- or MIC+ to VEE Common Mode Rejection Ratio Voltage Gain MIC+ or MIC- to LN Gain Variation with Frequency at f=300Hz and f=3400Hz Gain Variation with Temperature at -25C and +75C
SYMBOL
MIN
TYP
MAX
UNIT
Zi Zi kCMR Iline=15mA R7=68k w.r.t.800Hz
64 32 82
k k dB
Gv Gvf
50.5
52.0 +-0.2
53.5
dB dB
w.r.t.25C without R6; Iline=50mA Dual-tone multi-frequency input DTMF (pin 11) Input impedance Voltage Gain from DTMF to LN Iline=15mA R7=68k Gain Variation with Frequency at f=300Hz and f=3400Hz w.r.t.800Hz Gain Variation with Temperature at -25C and +75C w.r.t.25C Iline=50mA
GvT Zi Gv Gvf 24
+-0.2 20.7 25.5 +-0.2 27
dB k dB dB
GvT
+-0.2
dB
Gain Adjustment GAS1 and GAS2 (pins 2 and 3)
Gain Variation of the Transmitting Amplifier by Varying R7 between GAS1 and GAS2 Sending Amplifier Output LN (pin 1) Output Voltage
Gv Iline=15mA THD=10% Iline=4mA THD=10% Iline=15mA; R7=68k; 200 between MIC- and MIC+; psophometrically weighted
-8
0
dB
VLN(rms) VLN(rms)
1.7
2.3 0.8
V V
Noise output voltage
VNO(rms) Zi Zo
-69 21 4
dBmp k
Receiving Amplifier Input IR (pin 10)
Input impedance
Receiving Amplifier Output QR (pin 4)
Output Impedance Voltage gain from IR to QR Iline=15mA; RL(from pin 9 to pin 4 )=300
Gv
29.5
31
32.5
dB
UTC
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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS (continued)
PARAMETER
Gain Variation with Frequency at f=300Hz and f=3400Hz Gain Variation with Temperature at-25C and +75C
TEST CONDITIONS
w.r.t.800Hz w.r.t.25C without R6 Iline=50mA sinwave drive; Ip=0mA;THD=2% R4=100k Iline=15mA RL=150 RL=450 THD=10% R4=100k RL=150 Iline=4mA Iline=15mA R4=100k IR open-circuit psophometrically weighted RL=300
SYMBOL
Gvf
MIN
TYP
0.2
MAX
UNIT
dB
GvT
+-0.2
dB
Output Voltage
VO(rms) VO(rms)
0.22 0.3
0.33 0.48
V V
Output Voltage
VO(rms)
15
mV
Noise Output Voltage
VNO(rms)
50
V
Gain adjustment GAR (pin 5)
Gain Variation of Receiving Amplifier Achievable by Varying R4 between GAR and QR
Gv
-11
0
dB
Mute Input (pin 12)
Input Voltage(HIGH) Input Voltage(LOW) Input Current VIH VIL IMUTE MUTE=LOW MUTE=LOW R4=100k RL=300 Gv 1.5 8 70 VCC 0.3 15 V V A dB
Reduction of Gain
MIC+ or MIC- to QR Voltage Gain from DTMF to QR
Gv
-19
dB
Automatic Gain Control Input
AGC ( pin 15)
Controlling the Gain from lR to QR and the Gain from MIC+/MICto LN;R6 between AGC and VEE R6=110k Gain Control Range Iline=70mA Highest Line Current for Maximum Gain Minimum Line Current for Minimum Gain
Gv Iline Iline
-5.8 23 61
dB mA mA
UTC
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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION Supply: VCC, LN, SLPE, REG and STAB
Power for the UTC TEA1062N/TEA1062AN and its peripheral circuits is usually obtained from the telephone line. The IC supply voltage is derived from the line via a dropping resistor and regulated by the UTC TEA1062N/TEA1062AN,The supply voltage Vcc may also be used to supply external circuits e.g. dialling and control circuits. Decoupling of the supply voltage is performed by a capacitor between Vcc and VEE while the internal voltage regulator is decoupled by a capacitor between REG and VEE. The DC current drawn by the device will vary in accordance with varying values of the exchange voltage(Vexch), the feeding bridge resistance(Rexch) and the DC resistance The UTC of the telephone line(Rline). TEA1062N/TEA1062AN has an internal current stabilizer operating at a level determined by a 3.6k resistor connected between STAB and VEE( see Fig.8). When the line current(Iline) is more than 0.5 mA greater than the sum of the IC supply current ( Icc) and the current drawn by the peripheral circuitry connected to VCC(lp) the excess current is shunted to VEE via LN. The regulated voltage on the line terminal(VLN) can be calculated as: VLN=Vref+ISLPE*R9 or; 3 VLN=Vref+[(Iline - ICC - 0.5*10- A)Ip]*R9 where:Vref is an internally generated temperature compensated reference voltage of 3.7V and R9 is an external resistor connected between SLPE and VEE. In normal use the value of R9 would be 20. Changing the value of R9 will also affect microphone gain, DTMF gain,gain control characteristics, side tone level, maxmimum output swing on LN and the DC characteristics (especially at the lower voltages). Under normal conditions, when ISLPE>=ICC+0.5mA +Ip, the static behaviour of the circuit is that of a 3.7V regulator diode with an internal resistance equal to that of R9.In the audio frequency range the dynamic impedance is largely determined by R1.Fig.3 shows the equivalent impedance of the circuit. (with built-in FET source followers) can be used. Microphone arrangements are illustrated in Fig.10. The gain of the microphone amplifier can be adjusted between 44dB and 52dB to suit the sensitivity of the transducer in use. The gain is proportional to the value of R7 which is connected between GAS1 and GAS2. Stability is ensured by the external capacitors, C6 connected between GAS1 and SLPE and C8 connected between GAS1 and VEE. The value of C6 is 100pF but this may be increased to obtain a first-order low-pass filter. The value of C8 is 10 times the value of C6. The cut-off frequency corresponds to the time constant R7*C6.
Mute input (MUTE)
A LOW(UTC TEA1062N is HIGH) level at MUTE enables DTMF input and inhibites the microphone inputs and the receiving amplifier inputs; a HIGH(UTC TEA1062N is LOW) level or an open circuit does the reverse. Switching the mute input will cause negligible clickis at the telephone outputs and on the line. In case the line current drops below 6mA(parallal opration of more sets) the circuit is always in speech condition independant of the DC level applied to the MUTE input.
Dual-tone multi-frequency input (DTMF)
When the DTMF input is enabled dialling tones may be sent onto the line. The voltage gain from DTMF to LN is typically 25.5dB(when R7=68k) and varies with R7 in the same way as the microphone gain. The signalling tones can be heard in the earpiece at a low level(confidence tone).
Receiving amplifier (IR,QR and GAR)
The receiving amplifier has one input (IR) and a non-inverting output (QR). Earpiece arrangements are illustrated in Fig.11. The IR to QR gain is typically 31dB (when R4=100k). It can be adjusted between 20 and 31dB to match the sensitivity of the transducer in use. The gain is set with the value of R4 which is connected between GAR and QR.The overall receive gain, between LN and QR, is calculated by substracting the anti-sidetone network attenuation (32dB) from the amplifier gain. Two external capacitors, C4 and C7, ensure stability. C4 is normally 100pF and C7 is 10 times the value of C4. The value of C4 may be increased to obtain a first-order low-pass filter.The
Microphone inputs(MIC+ and MIC-) and gain pins (GAS1 and GAS2)
The UTC TEA1062N/TEA1062AN has symmetrical inputs. Its input impedance is 64k (2*32k) and its voltage gain is typically 52 dB (when R7=68k.see Fig.13). Dynamic, magnetic, piezoelectric or electret
UTC
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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
cut-off frequency will depend on the time constant R4*C4. The output voltage of the receiving amplifier is specified for continuous-wave drive. The maximum output voltage will be higher under speech conditions where the peak to RMS ratio is higher. Example The balance impedance Zbal at which the optimum suppression is present can be calculated by: Suppose Zline = 210+(1265//140nF) representing a 5km line of 0.5 mm diameter, copper, twisted pair cable matched to 600(176/km;38nF/km). When k=0.64 then R8=390,Zbal=130+(820//220nF). At line currents below 9mA the internal reference voltage is automatically adjusted to a lower value(typically 1.6V at 1mA) This means that more sets can be operated in parallel with DC line voltages (excluding the polarity guard) down to an absolute minimum voltage of 1.6V. With line currents below 9mA the circuit has limited sending and receiving levels. The internal reference voltage can be adjusted by means of an external resistor(RVA). This resistor when connected between LN and REG will decrease the internal reference voltage and when connected between REG and SLPE will increase the internal reference voltage. Current(Ip) available from VCC for peripheral circuits depends on the external components used. Fig.9 shows this current for VCC > 2.2V. If MUTE is LOW (1062 is HIGH) when the receiving amplifier is driven the available current is further reduced. Current availability can be increased by connecting the supply IC(1081) in parallel with R1, as shown in Fig.16(c), or, by increasing the DC line voltage by means of an external resistor(RVA) connected between REG and SLPE.
Automatic gain control input (AGC)
Automatic line loss compensation is achieved by connecting a resistor(R6) between AGC and VEE. The automatic gain control varies the gain of the microphone amplifier and the receiving amplifier in accordance with the DC line current. The control range is 5.8dB which corresponds to a line length of 5km for a 0.5mm diameter twisted pair copper cable with a DC resistance of 176/km and average attenuation of 1.2dB/km. Resistor R6 should be chosen inaccordance with the exchange supply voltage and its feeding bridge resistance(see Fig.12 and Table 1). The ratio of start and stop currents of the AGC curve is independent of the value of R6. If no automatic line loss compensation is required the AGC may be left open-circuit. The amplifier, in this condition, will give their maximum specified gain.
Side-tone suppression
The anti-sidetone network, R1//Zline, R2, R3, R8, R9 and Zbal,(see Fig.4) suppresses the transmitted signal in the earpiece. Compensation is maximum when the following conditions are fulfilled: (a) R9*R2=R1[R3+(R8//Zbal)]; (b) [Zbal/(Zbal+R8)]=[Zline/(Zline+R1)]; If fixed values are chosen for R1, R2, R3 and R9 then condition(a) will always be fullfilled when R8/ZballR3. To obtain optimum side-tone suppression condition(b) has to be fulfilled which results in: Zbal=(R8/R1) Zline=k*Zline where k is a scale factor; K=(R8/R1). The scale factor (k), dependent on the value of R8, is chosen to meet following criteria: (a) Compatibility with a standard capacitor from the E6 or E12 range for Zbal, (b)Zbal//R8R3 fulfilling condition (a) and thus ensuring correct anti-sidetone bridge operation, (c) Zbal+R8R9 to avoid influencing the transmitter gain. In practice Zline varies considerably with the type and length. The value chosen for Zbal should therefore be for an average line length thus giving optimum setting for short or long lines.
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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
LN Leq Rp REG Vref R9
20
R1 VCC C1
C3
4.7 F
100 F
Rp=16.2k Leq=C3*R9*Rp
VEE
Fig.3 Equivalent impedance circuit
The anti-sidetone network for the UTCTEA1062N/TEA1062AN family shown in Fig.4 attenuates the signl received from the line by 32 dB before it enters the receiving amplifier. The attenuation is almost constant over the whole audio frequency range. Fig.5 shows a convertional Wheatstone bridge anti-sidetone circuit that can be used as an alternative. Both bridge types can be used with either resistive or complex set impedances.
R1 R2
Zline
Zline
R1
R2
im VEE
R9 R8
IR
R3 Rt
im VEE
R9 R8
IR
Rt
SLPE
Zbal
RA SLPE
Fig 4 Equivalent circuit of UTC TEA1062N/TEA1062AN anti-sidetone bridge
Equivalent circuit of an anti-sidetone network in a wheatstone bridge configuration
Fig 5
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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
Iline 150
(mA)
130
110
(1)
90
(2)
70
(3) (4) Tamb Ptot
50
(1) 45C (2) 55C (3) 65C (4) 75C
2 4 6 8 10 12
1068mW 934mW 800mW 666mW
30
VLN-VSLPE(V)
Fig.6 UTC TEA1062N/TEA1062AN safe operating area
Rline
Iline
R1
ISLPE + 0.5mA
LN
VCC 0.5mA C1
PERIPHERAL CIRCUITS
Rexch
DC AC
REG
STAB
SLPE
VEE
Vexch C3
R5
ISLPE
R9
Fig.8 Supply arrangement
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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
2.4
Ip
(mA)
a
b
1.6
0.8
0 0 1 2 3 4
(a) Ip=2.1mA (b) Ip=1.7mA Iline=15mA at VLN=4V R1=620 and R9=20 Vcc(V)
5
Fig.9
Typical current Ip available from Vcc peripheral circuitry with Vcc>=2.2V.
curve (a) is valid when the receiving amplifier is not driven or when MUTE =LOW(UTC TEA1062N is HIGH) .curve(b) is valid when MUTE=HIGH(UTC TEA1062N is LOW) and the receiving amplifier is driven; Vo(rms)=150mV,RL=150.The supply possibilities can be increased simply by setting the voltage drop over the circuit VLN to a high value by means of resistor RVA connected between REG and SLPE.
7 MIC+ (1) 7 13 7 MIC+ 6 MIC6 MICMIC+
VCC
VEE
9
6
MIC-
(a)
(b)
(c)
Fig. 10 Alternative microphone arrangement (a) Magnetic or dynamic microphone. The resistor marked(1) may be connected to decrease the terminating impedance. (b) Electret microphone. (c) Piezoelectric microphone.
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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
QR 4
(1) QR 4
QR 4
(2)
VEE 9
VEE 9
VEE 9
(a)
(b)
Fig.11 Alternative receiver arrangement
(c)
(a) Dynamic earpiece. (b) Magnetic earpiece.The resistor marked(1) may be connected to prvent distortion(inductive load) (c) Piezoelectric earpiece.The earpiece marked(2) is requirred to increase the phase margin (capacitive load) Fig.12 Variation of gain with line urrent,with R6 as a parameter.
Gv (dB) R6= 0 -2 -4 -6 0 20 40 60 80 100 120 140 Iline (mA)
R9=20 (1) R6= 78.7k
(1) (2) (3)
(2) R6= 110k (3) R6= 140k
Rexch()
400
600 R6(k)
800
1000
36
100 140
78.7 110
x 93.1
x 82
Vexch(V)
Table 1
48
x x 60 120 102 Values of resistor R6 for optimum line loss compensation,for various usual values of exchange supply vloltage(Vexch) and exchange feeding bridge resistance(Rexch);R9=20.
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UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
R1 620 13 10 IR VCC 7 MIC+
Vi C1 100 F
1
LN QR
100 F
4 5
R4 100k
C4 100pF C7 1nF
RL 600 10 TO 140 mA
6 MIC11 DTMF 12 MUTE
GAR
2 GAS1
Vo
10 F
GAS2 3 VEE REG AGC STAB SLPE
R7 68k
C8 1nF C6 100pF
9
Vi
C3 4.7 F
14
R6
15 8
R5 3.6k
16
R9 20
Fig.13 Test circuit defining voltage gain of MIC+,MIC- and DTMF inputs. Voltage gain is defined as : GV=20*log(|VO/Vi|).For measuring the gain from MIC+ and MIC- the MUTE input should be HIGH(UTC TEA1062N is LOW) or open-circuit, for measuring the DTMF input MUTE should be LOW(UTC TEA1062N is HIGH) .Inputs not under test should be open-circuit.
R1=620 13
VCC
1
LN QR
100 F C2
10 IR 7 MIC+
C1 100F
4
R4 100k
ZL 600 10 TO 140 mA
GAR 5 GAS1 2 GAS2 3 SLPE
C4 Vo 100pF C7 1nF
6 MIC11 DTMF 12
10 F
R7 68k
C8 1nF C6 100pF
MUTE
VEE REG AGC STAB
9
Vi
C3 4.7 F
14
R6
15 8
R5 3.6k
16
R9 20
Fig.14 Test circuit for defining voltage gain of the receiving amplifier. Voltage gain is defined as: GV=20*log(|VO/Vi|).
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QW-R108-011,A
UTC TEA1062N / TEA1062AN LINEAR INTEGRATED CIRCUIT
R1 620 R10 130
BAS11 (x2) BZX79 C12
R2 132k
C5 100nF 10 IR
1 LN
13 VCC
C1 100 F
Telephone Line
C2
BZW14 (x2)
R4 R3 3.92k C7 1nF
QR C4 100pF 5 GAR 7 6
4
UTC TEAI062N UTC TEA1062AN
DTMF
11 From dial and control circuits
12
MIC+ MICSLPE 16 GAS1 2 GAS2 3 REG 14 AGC 15
MUTE
R8 390
C6 100pF
STAB VEE 8 9
R7 RVA(R16.R14) R5 3.6k
Zbal
R9 20
C8 1nF
C3 4.7 F
R6
Fig.15 Typical application of the UTC TEA1062AN ,shown here with a piezoelectric earpiece and DTMF dialling. The bridge to the left ,the Zener diode and R10 limit the current into the circuit and the voltage across the circuit during line transients.Pulse dialling or register recall required a different protection arrangement. The DC line voltage can be set to a higher value by resistor RVA(REG to SLPE).
LN
VCC DTMF
VDD DTMF
CARDLE CONTRAT
UTC TEA1062AN
MUTE VEE
dialling circuit
M1 VSS DP/FL
TELEPHONE LINE
BSN254A
Fig.16
Typical applications of the UTC TEA1062N/TEA1062AN (simplified) The dashed lines show an optional flash (register recall by timed loop break).
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